Integrated Digital Time-to-Digital Converters

Digital delay time TDC's are integrated circuits for high precision time interval measurement and do this without any analog components. They became real thanks the to innovations in semiconductor technology made over years. They use the propagation delays of simple logical gates (i.e. inverters) for fine quantization of time intervals. Due to the enormous achievements in signal speed, especially in the CMOS sector, it has become possible to implement such TDC's in standard CMOS technology with a resolution in the picosecond range. Nowadays we can integrate system solutions into a single chip that are efficient, power saving, space saving and none the less low price.

Digital TDCs can be split into two groups

• Absolute delay time TDC's
  
• Relative delay time TDC's
  

Absolute Delay Time TDC

This type of TDC uses the absolute propagation time of signals through simple logical elements for fine quantisation of time intervals.

In other words, it determines how many inverter cycles the measured time interval consists of. The figure shows the principle of operation. Clever circuit set-ups, redundant elements and special layout methods on the chip enable the exact reconstruction of the number of basic time intervals. The resolution strictly dependends upon the basic delay time in the chip. Resolutions in the range of 14 -100 ps can be achieved by a simple set-up of the measuring core and the use of a state-of-the art CMOS process. The propagation delay itself depends on temperature and supply voltage. Therefore the measured value must be calibrated. This is done by measuring one and two periods of a reference oscillator. Ideally this measurement and the following calculation is done by the TDC itself.

Absolute delay time TDCs have the following advantage:

• The delay time of the inverter can be precisely adjusted and stabilized by using a phase controlled loop (PLL). It is indeoendent from supply voltage and temperature.
  

Relative Delay Time TDC

While for the absolute delay approach the resolution possible depends on the speed of the semiconductor process used, we can skip this limit by using a relative delay time solution. As indicated by the name, this type of TDC measures a relative delay difference between two delay chain elements to get fine quantization.

With the help of a specific circuit set-up, the resolution becomes identical to the difference between the two running times t1 and t2 , and it is possible to reach delay values far under the gate delay time.

Principally, any resolution should be possible, but in reality there are limits due to quantization errors and some other sources of error. Practically a resolution of approximately 1/5th of the gate delay time is realistic. Using modern CMOS technology, this is in the 10-15 ps range.

An excellent differential non-linearity addresses this solution to specific measurement tasks, and wherever this parameter plays a major role, this type of TDC might be used.

In many cases the use of an absolute delay time TDC is questionable or almost impossible. When implementing a quartz-accurate adjustment of the resolution, or when multi-hit capability is required, absolute delay time TDC's are the better choice (relative delay TDCs have limited double pulse resolution since this measuring mode requires a conversion time, resulting in a relatively long lag time).